1. Field of the Invention
The present invention relates to a pattern layout designing method, a semiconductor device manufacturing method, and a computer program product.
2. Description of the Related Art
In recent years, demands for refining of semiconductor elements are increasing. To form a fine pattern on a semiconductor substrate, it is conceivable to apply double patterning technologies or phase shift mask technologies to perform photolithography.
As one of the double patterning technologies, there is a technology for splitting a photomask of one layer of LSI pattern, which is collectively exposed in a photolithography process in the past, into two photomasks and alternately exposing patterns on photomasks, which are originally adjacent to one another, twice to thereby form patterns having fine pitches that cannot be formed by performing exposure once on a semiconductor substrate. As one of the phase shift mask technologies, there is a technology for alternately arranging phase shifters in adjacent translucent patterns on a photomask to thereby alternately shift phases of lights passing through the patterns 0 degree and 180 degrees and making an intensity profile of light focused on a resist steep to improve the resolution of a pattern formed on the resist.
When the double patterning technology is applied, patterns need to be classified into a type exposed with a first photomask and a type exposed with a second photomask. When the phase shift mask technology is applied, patterns need to be classified into a type in which the phase shifters are arranged and a type in which the phase shifters are not arranged. Regardless of which of the technologies is applied, patterns need to be classified (sorted) into two types such that adjacent patterns on a photomask belong to different types. However, in principle, a section where adjacent patterns belong to the same type (a conflict) occurs. Therefore, there is a demand for a technology for detecting and removing, at a stage when a layout design drawing of a mask pattern or a design pattern (hereinafter, the mask pattern design drawing and the design pattern design drawing are collectively referred to as pattern layout design drawing) is created, a structure in which such an unclassifiable section occurs.
To meet the demand, for example, Japanese Patent No. 3307313 discloses a technology for detecting a section where an odd number of patterns are annularly arranged in a fine section (an odd number loop) and rearranging a part of patterns forming the odd number loop to remove a conflict.
However, recently, semiconductor integrated circuits are complicated. Therefore, an odd number loop connected to other loops is often formed in a fine section of a pattern of a mask layout design drawing for a photomask. In such an odd number loop connected to a plurality of loops, the number of rearrangement target patterns may increase depending on selection of rearrangement target patterns. When the number of rearrangement target patterns increases, a design load increases according to the increase. Therefore, it is important to efficiently select rearrangement target patterns such that the number of rearrangement target patterns decreases. However, Japanese Patent No. 3307313 does not disclose a method of efficiently selecting rearrangement target patterns.